1. Field of the Invention
The present invention pertains to semiconductor device fabrication and to a method for the post-etch treatment of etched metal-comprising features, to prevent corrosion of the etched feature surface.
2. Brief Description of the Background Art
In the multi level metallization architecture used in present day semiconductor devices, aluminum is generally used as the material of construction for interconnect lines and contacts. Although aluminum offers a number of advantages in ease of fabrication, as integrated circuit designers focus on transistor gate velocity and interconnect line transmission time, it becomes apparent that copper is the material of choice for the next generation of interconnect lines and contacts. The resistivity of copper is about 1.4 .mu..OMEGA.cm, which is only about half of the resistivity of aluminum.
There are two principal competing technologies under evaluation by material and process developers working to enable the use of copper. The first technology is known as damascene technology. In this technology, a typical process for producing a multilevel structure having feature sizes in the range of 0.5 micron (.mu.m) or less would include: blanket deposition of a dielectric material; patterning of the dielectric material to form openings; deposition of a diffusion barrier layer and, optionally, a wetting layer to line the openings; deposition of a copper layer onto the substrate in sufficient thickness to fill the openings; and removal of excessive conductive material from the substrate surface using chemical-mechanical polishing (CMP) techniques. The damascene process is described in detail by C. Steinbruchel in "Patterning of copper for multilevel metallization: reactive ion etching and chemical-mechanical polishing", Applied Surface Science 91 (1995) 139-146.
A particular problem with the damascene process is that the CMP techniques used to remove excess copper from the dielectric surface after deposition create problems. Copper is a soft material which tends to smear across the underlying surface during polishing. "Dishing" of the copper surface may occur during polishing. As a result of dishing, there is variation in the critical dimensions of conductive features. Particles from the slurry used during the chemical mechanical polishing process may become embedded in the surface of the copper and other materials surrounding the location of the copper lines and contacts. The chemicals present in the slurry may corrode the copper, leading to increased resistivity and possibly even corrosion through an entire wire line thickness. Despite the number of problems to be solved in the damascene process, this process has been viewed in the industry as more likely to succeed than a patterned copper etch process, because of the difficulty in preventing the corrosion of copper both during the etch process and post etch, during subsequent processing.
The competing technology is one which involves the patterned etch of a copper layer. In this technology, a typical process would include deposition of a copper layer on a desired substrate (typically a dielectric material having a barrier layer on its surface); application of a patterned hard mask or photoresist over the copper layer; pattern etching of the copper layer using wet or dry etch techniques; and deposition of a dielectric material over the surface of the patterned copper layer, to provide isolation of conductive lines and contacts which comprise various integrated circuits. An advantage of the patterned etch process is that the copper layer can be applied using sputtering techniques well known in the art. The sputtering of copper provides a much higher deposition rate than the evaporation or CVD processes typically used in the damascene process, and provides a much cleaner, higher quality copper film than CVD. Further, it is easier to etch fine patterns into the copper surface and then deposit an insulating layer over these patterns than it is to get the barrier layer materials and the copper to flow into small feature openings in the top of a patterned insulating film.
However, patterned etch of a copper layer is more difficult than patterned etch of an aluminum layer, due to the chemical and physical properties of the copper film. For example, although copper reacts with chlorine at low temperature as aluminum does, the product of the reaction is not as volatile as the reaction product with aluminum. This causes copper film to corrode rather than etch when subjected to conditions similar to those used to etch aluminum. An undesired reaction can easily extend to a location within a copper layer. In fact, copper features have been observed to have smooth sidewalls outside but to have corroded interiors. To prevent the interior corrosion of pattern-etched copper films, we first developed methods of protecting the etched copper surface of copper features during the etch process. These methods are described in the following patent applications: U.S. Ser. No. 08/891,410 of Ye et al., titled "Patterned Copper Etch For Micron And Submicron Features Using Enhanced Physical Bombardment", filed Jul. 9, 1997; U.S. Ser. No. 08/911,878 of Ye et al., titled "Copper Etch Using HCl and HBr Chemistry", filed Aug. 13, 1997; U.S. Ser. No. 09/042,146 of Ye et al. titled "Process For Copper Etch Back", filed Mar. 13, 1998; and U.S. Ser. No. 09/130,893 of Ye et al., titled "Method Of Etching Copper For Semiconductor Devices", filed Aug. 7, 1998. The subject matter of these applications is hereby incorporated by reference in its entirety.
Although we were able to obtain etched copper features which exhibited minimal to no corrosion at the end of the etch process, we discovered that corrosion could occur during subsequent device processing steps. In order to achieve good electrical critical dimension (ECD) control and electro migration (EM) control, the etched copper features must be kept free of corrosion, including oxidation, must be prevented. We began work to determine how best to protect the etched copper surface until such time that a protective layer or coating is applied over the copper surface during subsequent processing steps which typically follow a pattern etching step.
Others working in the art have tried various methods of treating the copper surface after pattern etching to remove contaminants from the copper surface which were viewed as causing post-etch corrosion of the copper. Harold F. Winters, in his article "The etching of Cu(100) with Cl.sub.2, J. Vac. Sci. Technol. A3(3), May/June 1985, pp. 786-790, describes etch products, surface chemistry and product desorption mechanisms for interaction of Cl.sub.2 with Cu(100). The dominant etch product is said to be Cu.sub.3 Cl.sub.3 when the substrate temperature is less than about 580.degree. C. and CuCl when the substrate temperature is greater than 650.degree. C. Exposure of Cu(100) to Cl.sub.2 at temperatures below 150.degree. C. is said to lead to the growth of a copper chloride layer whose thickness increases linearly with time for exposures greater than approximately 1000 langmuirs. The rate of growth of the chloride layer decreases with increasing temperature. The chloride is said to desorb as Cu.sub.3 Cl.sub.3, with zero order kinetics. The zero order kinetics suggest that the quantity of chlorine on the immediate surface remains constant until the chlorine in the bulk is depleted. The author concludes that etching is simply a "compound growth"--evaporation reaction. Ion bombardment is said to suppress the etch rate which is thought to be a consequence of ion-induced dissociation of Cu.sub.3 Cl.sub.3 and possibly a decreased concentration of chlorine in the surface region.
An example of the surface treatment-of copper to prevent corrosion is provided in Japanese Patent Application No. 61041775A, published on Feb. 28, 1986. The abstract for this application discloses a surface treatment of copper using an aqueous solution containing copper ions, chelating agent, reducing agent, hydroxide ions and at least one zirconia and/or bismuth compound.
Another example of a treatment to remove chlorides and fluorides remaining after the etch of a conductive layer is provided in U.S. Pat. No. 4,668,335 to Mockler et al., issued May 26, 1987. In Mockler et al., the preferred embodiments pertain to the etching of aluminum, aluminum-copper, and aluminum-copper-silicon alloys. After the etch step, the workpiece (wafer) is immersed in a strong acid solution, followed by a weak base solution after the etch of an aluminum-copper alloy, to remove residual chlorides and fluorides remaining on the etched surface.
A further example of the removal of corrosive materials from the etched surface is provided in U.S. Pat. No. 5,200,031 to Latchford et al., issued Apr. 6, 1993. In Latchford et al, a process is described for removing a photoresist remaining after one or more metal etch steps which also removes or inactivates chlorine-containing residues, to inhibit corrosion of remaining metal for at least 24 hours. The etched metal layer is said to comprise aluminum, titanium, tungsten, etc. The integrated circuit structure (wafer) is said to be removed from the metal etch chamber and placed in a vacuum stripping chamber, unless the same chamber is to be used for both processes. The wafer temperature, as it emerges from the metal etch chamber is described as being about 100.degree. C. The wafer temperature during the stripping process is maintained within a range of from about. 100.degree. C. to about 400.degree. C., preferably from about 200.degree. C. to about 300.degree. C. When the wafer entering the stripping process is at 100.degree. C. and it is desired to carry out the stripping process at a higher temperature, the wafer temperature may be ramped up to the desired temperature at a rate of about 10.degree. C. per second while the first stripping step is being carried out. In the first stripping step, NH.sub.3 gas is flowed through a microwave plasma generator into a stripping chamber containing the workpiece; in the second stripping step, O.sub.2 gas (and optionally NH.sub.3 gas), is flowed through the microwave plasma generator into the stripping chamber.
U.S. Pat. No. 5,244,535 to Ohtsuka et al., issued Sep. 14, 1993, describes a method for making a semiconductor device which includes formiing of an insulation layer on top of a conduction layer adhered to a semiconductor substrate; forming contact holes by etching the insulation layer with a fluorine-based gas; and converting a gas containing nitrogen to a plasma and using the obtained plasma to treat at least the aforementioned contact holes. In particular, the conductive layer is an aluminum alloy (containing 2% copper); the post-etch plasma treatment of the conductive layer surface is conducted with a nitrogen gas plasma at a temperature of about 12.degree. C. for a period of about 15 seconds, after which the substrate is exposed to air.
U.S. Pat. No. 5,302,241 to Cathey, Jr., issued Apr. 12, 1994, describes the post etching treatment of semiconductor devices. After the etching of a semiconductor device, prior to removing the etched semiconductor from the etching area, a passivating agent comprising silicon tetrafluoride is introduced into the etching area. The passivating agent reacts with any reactive chemical compound associated with the semiconductor to inhibit corrosion of the semiconductor device. The inhibited reactive chemical composition, which is typically in the gas phase, is then pumped out of the etch area. The preferred embodiment is an aluminum or aluminum alloy layer, where the etchant is a halogen containing material, preferably chlorine gas or HCl, which is said to cause corrosion of the aluminum after it is removed from the etching area. The passivating agent is a gaseous SiF.sub.4 plasma, which forms an inhibited reactive chemical compound by replacing the chlorinated products to provide sidewall passivation, where the byproducts of the passivation reaction are then removed from the etching area. There is no mention of the substrate temperature during the post-etch treatment.
Japanese patent application number 9315119A, published Feb. 2, 1993, describes a semiconductor device manufacturing method used in VLSI circuit fabrication which incorporates vacuum storage processing followed by plasma processing by chlorofluoro carbon compound gas.
Andreas Bertz et al. in their article entitled "Effects of the biasing frequency on RIE of Cu in a Cl.sub.2 -based discharge", Elsevier Applied Surface Science 91-(1995) pp. 147-151 describe the use of sidewall forming additives such as CH.sub.4 within the etchant source gas as a means for overcoming a rim-like copper attack at the interface between the masking material and the copper surface. However, the addition of only 4 sccm of CH.sub.4 as a sidewall passivating additive is said to have led to a remarkable etch rate reduction due to the deposition of a thin surface-covering film.
Despite the number of methods described in the art for post-etch treatment to reduce corrosion of etched copper features, the corrosion problem remained, to an extent that those skilled in the art considered the damascene process to be the process of choice for the formation of patterned copper features in semiconductor devices. The post-etch treatment method of the present invention reduces or eliminates the corrosion problem on the surface of plasma etched copper features, so that plasma etching becomes the preferred method for the fabrication of patterned copper semiconductor features. In addition, the method is useful for the reduction of corrosion with respect to other plasma-etched metal-comprising features such as aluminum, tungsten, PZT (Pb(Zr.sub.1-x Ti.sub.x)O.sub.3, and BST (Ba,Sr)TiO.sub.3, for example, and not by way of limitation.